Design and VHDL Implementation of Synchronous TDM controller for on chip data communication

Abstract

The objective of this research article is to design and VLSI implementation of synchronous TDM controller as soft IP core for on chip data communication, which multiplexes data from 32-line source and carry in repetitive frames, each frame of 32 channels (or time slots). The main aim is to design TDM controller so that the wide range of local processors or IP cores can communicate with TDM controller without disturbing the internal activities of other devices interfaced to the TDM controller and also to reduce the area overhead, cross talk, cost, and increase the efficiency of the processors or chip. Synchronous TDM systems is based on the notion of a fixed duration frame, which in turn is divided into a constant number of equally spaced intervals of time known as time slots (TS). Several data sources share a common transmission medium simultaneously. The “Synchronous Time Division Multiplexing” is selected because it is simple, easier, and it can be implemented in hardware without requirement of software are its major advantages. The TDM controller provides an interface to the 32-bit local processor or IP core. This TDM controller is fully compliant to the Wishbone specification. The device supports Wishbone Address bus of (3-bit), Wishbone Data bus of (32-bit), Wishbone Read, Write and Block Transfer Cycles. The device has two inbuilt single port 32x8 bit RAMs to facilitate easy interfacing with 32-bit local processors. The Half duplex mode of communication is used. The TDM Controller has been designed using top-down approach and then the design has been implemented using Xilinx Project Navigator as the designing tool and ModelSim simulator provides the post layout simulations. The design entry used is VHDL, which was written in Xilinx project navigator and then simulated using ModelSim.